Can We Really Do Without the Support of Formal Methods in the Verification of Large Designs? - Technical Paper from DAC 2005
STMicroelectronics
Paper by Umberto Rossi.
From the IC industry’s standpoint, the incubation of formal methods for deployment in EDA verification flows has been very long and is still occurring. Formal methods applied at functional verification have interpreted different roles - e.g. are they good for proving correctness or for catching bugs in deep behavioral corner cases - have played with different techniques - e.g. BDD’s, SAT, ATPG, symbolic - and finally have federated with simulation for the purpose of achieving coverage closure. Further, in the last 10 years a fair number of start-up’s have emerged, that have been acquired by major vendors in the meantime, and new start-up’s have been appearing also this year.
What are the reasons that make the IC industry to accept an unusually long maturation period of the formal methodology & tools and the EDA vendors to put money in the basket of their developments?
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